FIG. 1 of the accompanying drawings illustrates a known type of switched capacitor digital/analogue converter (DAC) for converting an input n-bit digital code to a corresponding analogue voltage output. The digital-to-analogue converter comprises n-capacitors C1, . . . , Cn with the capacitance Ci of each ith capacitor preferably being equal to 2(i-1) C1. The DAC further comprises a terminating capacitor CTERM connected between the input of a unity gain buffer 1 and ground. The first electrodes of the capacitors C1, . . . , Cn are connected together and to the first terminal of the terminating capacitor CTERM. The second terminal of each of the capacitors C1, . . . , Cn is connected to a respective switch, such as 2, which selectively connects the second electrode to a first or second reference voltage input V1 or V2 in accordance with the state or value of a corresponding bit of the input code. The output of the buffer 1 drives a capacitive load CLOAD, for example in the form of a data line or column electrode of an active matrix of a liquid crystal device.
The DAC has two phases of operation, namely a resetting or “zeroing” phase and a converting or “decoding” phase, controlled by timing signals which are not illustrated in FIG. 1. During the zeroing phase, the first and second electrodes of the capacitors C1, . . . , Cn and the first electrode of the terminating capacitor CTERM are connected together, and to the first reference voltage input V1 by an electronic switch 3. The capacitors C1, . . . , Cn are therefore discharged so that the total charge stored in the DAC is equal to V1CTERM.
During the decoding phase, the second electrode of each capacitor Ci is connected to the first reference voltage input V1 or to the second reference voltage input V2 according to the value of the ith bit of the input code. The charge stored in the DAC is given by:
                    Q        =                                            ∑              i                        ⁢                                          b                i                            ⁢                                                C                  i                                ⁡                                  (                                                            V                      DAC                                        -                                          V                      2                                                        )                                                              +                                    ∑              i                        ⁢                                          (                                  1                  -                                      b                    i                                                  )                            ⁢                                                C                  i                                ⁡                                  (                                                            V                      DAC                                        -                                          V                      1                                                        )                                                              +                                    V              DAC                        ⁢                          C              TERM                                                          (        1        )                            where bi is the ith bit of the input code and VDAC is the voltage at the first electrodes of the capacitors C1, . . . , Cn and CTERM. The output voltage is therefore given by:        
                              V          DAC                =                              V            OUT                    =                                                                                          ∑                    i                                    ⁢                                                            b                      i                                        ⁢                                          C                      i                                                                                                                                  ∑                      i                                        ⁢                                          C                      i                                                        +                                      C                    TERM                                                              ⁢                              (                                                      V                    2                                    -                                      V                    1                                                  )                                      +                          V              1                                                          (        2        )            
In general, Ci=2(i-1) C1 and C1=CTERM. This results in a set of output voltages which are linearly related to the input digital word.
The unity gain buffer 1 is provided in order to isolate the load capacitance from the DAC and to prevent it from affecting the conversion process. However, such buffers are a substantial source of power consumption, and in many applications it is desirable to eliminate the unity gain buffer 1.If the buffer 1 were to be omitted, the terminating capacitance would be increased by the addition of the load capacitance so that the maximum output voltage from the DAC would be given by:
                              V                      OUT            ⁡                          (              MAX              )                                      =                                                                              ∑                  i                                ⁢                                  C                  i                                                                                                  ∑                    i                                    ⁢                                      C                    i                                                  +                                  C                  TERM                                +                                  C                  LOAD                                                      ⁢                          (                                                V                  2                                -                                  V                  1                                            )                                +                      V            1                                              (        3        )            
Another example of a digital-to-analogue converter is a “bi-directional” digital-to-analogue converter, an example of which is shown in FIG. 2. The bi-directional DAC 32 of FIG. 2 includes a switched-capacitor digital-to-analogue converter having the general structure shown in FIG. 1, indicated schematically as component 4 in FIG. 2.
The converter is an n-bit converter, where n is an integer greater than one, and comprises an (n−1) bit bufferless switched capacitor converter 4 having first and second reference voltage inputs, labelled as V1 and V2 in FIG. 2, and an (n−1) bit digital input. An (n−1) bit selective inverter is provided for supplying to the (n−1) bit digital input the (n−1) least significant bits of an input code without inversion when the most significant bit (MSB) of the input code has a first value and with inversion when the most significant bit of the input code has a second value different from the first value. The (n−1) least significant bits of the input code are input to the switched-capacitor DAC 4 via selector switches 31 that can select either the bit or the inverted bit. The selector switches 31 are controlled by the most significant bit of the input code.
Each converter also has a switching arrangement for connecting the first and second reference voltage inputs to receive first and second reference voltages, respectively, when the most significant bit of the input code has the first value and to receive the second and first reference voltages respectively, when the most significant bit of the input code has the second value. Two different voltages VH, VL are input to the converter 4 of FIG. 2. The voltage input to the switched-capacitor digital-to-analogue converter 4 as the first reference voltage V1 can be set to be either VH or VL by means of a selector switch 30, and the voltage input to the switched-capacitor digital-to-analogue converter 4 as the second reference voltage V2 can be set to be either VL or VH by means of another selector switch 30′. The selector switches 30,30′ are controlled by the most significant bit (MSB) of the input code.
The unity-gain buffer 1 of FIG. 1 is omitted from the switched capacitor DAC 4 in the circuit of FIG. Accordingly, the term CTERM in equation (3) is replaced by CLOAD.
The DAC of FIG. 2 is designed to operate with
            ∑                            ⁢                  ⁢          C      i        =            C      TERM        .  Its operation is summarised in FIG. 3, and is as follows.
FIG. 3 shows the output voltage of the digital-to-analogue converter 32 of FIG. 2 as a function of the input code, for a case where the internal capacitance of the switched DAC 4 is equal to the load capacitance CLOAD. When the most significant bit of the input code is equal to zero, voltage VL is input to the switched-capacitor DAC 4 as the first reference voltage V1, and voltage VH is input as the second reference voltage V2. The (n−1) least significant bits bn-1 . . . b1 are not inverted. The analogue output of the DAC increases from an output of VL (for an input code of 00 . . . 00) to an output voltage of ½ (VL+VH) as the input code increases to 011 . . . 11. This is represented by the lower portion (or “arm”) of the output characteristic shown in FIG. 3, labelled “MSB=0”.
When the most significant bit of the input digital data is 1, the voltage VH is input to the switched capacitor DAC 4 as the first reference voltage V1, whereas the voltage VL is input as the second reference voltage V2. The (n−1) least significant bits are inverted by means of an inverting amplifier 5 before being input to the switched capacitor DAC 4. The analogue output voltage has a value VH for an input code of 11 . . . 11, and the output voltage decreases to ½ (VL+VH) as the input data decreases (that is, as the inverted least significant bit data increases) this is represented by the upper arm of the output characteristic shown in FIG. 3 (labelled “MSB=1”).
In FIG. 3, the two arms of the output meet at the Midpoint—that is, the output voltage for an input code of 011 . . . 11 is equal to the output voltage for an input code of 100 . . . 00.
The circuit of FIG. 2 is therefore known as a “bi-directional” DAC, because of the form of its output voltage characteristic shown in FIG. 3.
For correct operation of a bi-directional DAC, the internal capacitance of the switched capacitance DAC 4 must equal the load capacitance. However, while the internal capacitance of the switched capacitance DAC 4 can be well-controlled at the design stage, in many applications the load capacitance may not be precisely known, or the load capacitance may be subject to manufacturing tolerances so that its actual value may be different from its design value, or the value of the load capacitance may vary during operation. FIGS. 4 and 5 show the effect of a mis-match between the internal capacitance of the switched capacitance DAC 4 and a load capacitance.
FIG. 4 shows the output characteristic for a case where the internal capacitance of the switched capacitance DAC 4 (CDAC) is greater than the load capacitance. In this case, some output voltages are duplicated, such that two input data codes correspond to the same output voltage. In FIG. 4, for example, input data codes D1 and D2 (where D1 is not equal to D2) both produce the same output voltage of ½ (VL+VH).
Conversely, FIG. 5 shows the output characteristic for a case where CDAC<CLOAD. In this case, a range of output voltages do not correspond to any input data word. In FIG. 5, for example, no input codes will give an output voltage between V1 and V2. An output voltage can lie only in the voltage range between VL and V1 or the voltage range between V2 and VH.
Acknowledgement of the Prior Art
JP-A-11 027 147 describes a method of tuning the characteristics of one DAC to match the characteristics of another DAC (which is assumed to have the “correct” characteristics). It does not, however, address the problem of matching the internal capacitance of a DAC to an external load capacitance.